Platform Validation Lead / Manager

At Kandou, we are redefining the economics of AI infrastructure. Our mission is to democratise AI by significantly reducing the Total Cost of Ownership (TCO) of hardware systems — a critical barrier to scalable adoption.

Our proprietary MIMO-over-copper technology powers a high-performance, chiplet-based AI memory fabric that is both scalable and energy-efficient. Unlike traditional interconnects, our solution reduces power consumption significantly while preserving high bandwidth and ultra-low latency — unlocking unprecedented efficiency for AI training and inference at scale.

We are looking for a Platform Validation Lead/Manager

Location: Hyderabad, India

Responsabilities

• Own the Hyderabad platform-validation strategy for Ethernet Retimers, converting product, silicon, firmware and standards requirements into traceable test plans, entry and exit criteria, sample coverage and release decisions.

• Lead pre-silicon and post-silicon validation using simulation, FPGA or emulation and hardware-in-loop environments; drive first-silicon bring-up through power, clocks, boot, register access and module enumeration.

• Validate server and switch host integration, CMIS module-management state machines, I2C/SMBus and SPI mailbox flows, hot-plug, power sequencing, telemetry, diagnostics and fault recovery.

• Build automated regression, conformance and release-readiness workflows with requirements-to-test traceability, reproducible configurations, a known-failure catalog and evidence-based defect disposition.

• Lead and mentor the Hyderabad validation team; establish benches, equipment and lab processes, plan capacity, review results and remain hands-on in system-level debug and root-cause isolation.

• Partner across Hyderabad, Lausanne and Taiwan with SoC, DV, firmware, characterization, interoperability, product and field teams to correlate results and deliver qualified customer-ready releases.

Essential Experience

· 10+ years of silicon, system or platform validation experience on shipping SoCs, networking silicon, SerDes, retimers, PHYs, AEC/AOC or optical-module products.

· Direct ownership of at least one pre-silicon-to-post-silicon validation cycle, including first-silicon or board bring-up, qualification and release-readiness decisions.

· Hands-on system debug across silicon, boards, firmware, drivers and host applications, using JTAG, register traces, oscilloscopes, BERTs and related lab tools.

· Strong validation automation skills in Python and working C and/or C++ knowledge; experience with hardware-in-loop frameworks, CI, version control and reproducible test environments.

· Experience validating management and sideband interfaces such as CMIS, I2C//I3CSMBus, SPI, MDIO or MCTP, including state transitions, error paths, hot-plug and recovery behavior.