Senior SoC Design Verification Engineer

Quadric is redefining edge AI with the industry's first General Purpose Neural Processing Unit (GPNPU), enabling developers to run both neural network inference and conventional C++ code on a single programmable architecture. Our technology powers intelligent edge devices across automotive, industrial, robotics, and embedded systems.

Founded in 2016 and based in downtown Burlingame, California, Quadric is building the world's first supercomputer designed for the real-time needs of edge devices. Quadric aims to empower developers in every industry with superpowers to create tomorrow's technology, today. The company was co-founded by technologists from MIT and Carnegie Mellon, who were previously the technical co-founders of the Bitcoin computing company 21.

THE OPPORTUNITY

Quadric is building a revolutionary new processor-based SoC architecture. As a Senior SoC Design Verification Engineer, you will join the ground floor of our chip design team, taking technical leadership in architecting and building our SoC-level verification environment from scratch. You will collaborate closely with architects, hardware engineers, and software teams to ensure high quality and complete verification coverage for our next-generation GPNPU-based SoCs.

WHAT YOU'LL DO

TESTBENCH ARCHITECTURE & TEST PLAN DEVELOPMENT

- Architect and build novel, scratch-built testbenches for SoC-level verification of our GPNPU-based SoCs.

- Collaborate cross-functionally with architects, HW designers, and SW teams to document comprehensive verification test plans.

- Implement scalable testbenches using commercial Verification IP (VIP) and/or internal software utilities.

TEST EXECUTION & VERIFICATION COVERAGE

- Develop directed and random drivers, as well as assembly or C++ programs, to efficiently stress-test SoC subsystems and integration.

- Verify complex SoC subsystems, including 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).

- Leverage VCS and Verilog/C Co-Simulation environments alongside assembly programming and Python scripting to execute test suites.

- Track, analyze, and communicate verification progress across teams using functional and code coverage metrics.

WHAT SUCCESS LOOKS LIKE

Within your first 6–12 months, you'll:

- Build out and deploy a fully functional, scratch-built SoC-level UVM verification environment.

- Achieve target coverage metrics across all critical SoC subsystems and 3rd-party IP blocks.

- Establish robust co-simulation pipelines that validate HW/SW execution before tapeout.

WHAT WE'RE LOOKING FOR

REQUIRED

- Minimum 5+ years of dedicated design verification experience on complex SoC/ASIC designs.

- Deep expertise in UVM methodology and leading SoC-level verification practices.

- Proficiency in SystemVerilog or Verilog, assembly programming, and scripting languages like Python.

- Hands-on experience verifying SoC subsystems and 3rd-party IP (e.g., NoC, PCIe/UCIe, DDR).